mirror of
git://git.9front.org/plan9front/plan9front
synced 2025-01-12 11:10:06 +00:00
devusb: handle root-port reset delays outside of hci driver, rootport power control
We want to avoid long delays with interrupts disabled, so handle the delay from devusb/usbd. Do not expect SetFeatrue/PortEnable request, this is invalid by the usb standard. But some HCI's require setting enable bit in port status/ctrl register of rootports, so handle this internally. xhci, dwc and ohci have a power-power control bit, so implement standard Set/ClearFeature/PortPower in roothub, which allows us to control port on some rootports.
This commit is contained in:
cinap_lenrek
parent
ff65b74935
commit
2f12ad38ca
7 changed files with 227 additions and 259 deletions
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@ -27,9 +27,6 @@
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enum
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{
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USBREGS = VIRTIO + 0x980000,
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Enabledelay = 50,
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Resetdelay = 10,
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ResetdelayHS = 50,
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Read = 0,
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Write = 1,
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@ -936,61 +933,52 @@ seprintep(char *s, char*, Ep*)
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{
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return s;
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}
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enum {
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RW1C = Prtconndet | Prtena | Prtenchng | Prtovrcurrchng,
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};
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static int
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portenable(Hci *hp, int port, int on)
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static void
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portenable(Hci *hp, int, int on)
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{
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Ctlr *ctlr;
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Dwcregs *r;
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Ctlr *ctlr = hp->aux;
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Dwcregs *r = ctlr->regs;
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assert(port == 1);
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ctlr = hp->aux;
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r = ctlr->regs;
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dprint("usbdwc enable=%d; sts %#x\n", on, r->hport0);
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if(!on)
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r->hport0 = Prtpwr | Prtena;
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tsleep(&up->sleep, return0, 0, Enabledelay);
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dprint("usbdwc enable=%d; sts %#x\n", on, r->hport0);
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return 0;
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r->hport0 = (r->hport0 & ~RW1C) | Prtena;
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}
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static void
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portreset(Hci *hp, int, int on)
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{
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Ctlr *ctlr = hp->aux;
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Dwcregs *r = ctlr->regs;
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if(on)
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r->hport0 = (r->hport0 & ~RW1C) | Prtrst;
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else
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r->hport0 = (r->hport0 & ~RW1C) & ~Prtrst;
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}
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static void
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portpower(Hci *hp, int, int on)
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{
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Ctlr *ctlr = hp->aux;
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Dwcregs *r = ctlr->regs;
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if(on)
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r->hport0 = (r->hport0 & ~RW1C) | Prtpwr;
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else
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r->hport0 = (r->hport0 & ~RW1C) & ~Prtpwr;
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}
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static int
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portreset(Hci *hp, int port, int on)
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portstatus(Hci *hp, int)
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{
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Ctlr *ctlr;
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Dwcregs *r;
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Ctlr *ctlr = hp->aux;
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Dwcregs *r = ctlr->regs;
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int b, s;
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assert(port == 1);
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ctlr = hp->aux;
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r = ctlr->regs;
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dprint("usbdwc reset=%d; sts %#x\n", on, r->hport0);
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if(!on)
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return 0;
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r->hport0 = Prtpwr | Prtrst;
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tsleep(&up->sleep, return0, 0, ResetdelayHS);
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r->hport0 = Prtpwr;
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tsleep(&up->sleep, return0, 0, Enabledelay);
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s = r->hport0;
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b = s & (Prtconndet|Prtenchng|Prtovrcurrchng);
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if(b != 0)
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r->hport0 = Prtpwr | b;
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dprint("usbdwc reset=%d; sts %#x\n", on, s);
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if((s & Prtena) == 0)
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print("usbdwc: host port not enabled after reset");
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return 0;
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}
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static int
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portstatus(Hci *hp, int port)
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{
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Ctlr *ctlr;
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Dwcregs *r;
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int b, s;
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assert(port == 1);
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ctlr = hp->aux;
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r = ctlr->regs;
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s = r->hport0;
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b = s & (Prtconndet|Prtenchng|Prtovrcurrchng);
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if(b != 0)
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@ -1067,6 +1055,7 @@ reset(Hci *hp)
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hp->seprintep = seprintep;
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hp->portenable = portenable;
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hp->portreset = portreset;
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hp->portpower = portpower;
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hp->portstatus = portstatus;
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hp->shutdown = shutdown;
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hp->debug = setdebug;
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@ -43,7 +43,6 @@ enum
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Abortdelay = 1, /* delay after cancelling Tds (ms) */
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Tdatomic = 8, /* max nb. of Tds per bulk I/O op. */
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Enabledelay = 100, /* waiting for a port to enable */
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/* Queue states (software) */
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@ -339,7 +338,6 @@ struct Edpool
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struct Ctlr
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{
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Lock; /* for ilock; lists and basic ctlr I/O */
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QLock resetl; /* lock controller during USB reset */
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int active;
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Ctlr* next;
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int nports;
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@ -950,7 +948,6 @@ seprintep(char* s, char* e, Ep *ep)
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case Tctl:
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cio = ep->aux;
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s = seprintio(s, e, cio, "c");
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s = seprint(s, e, "\trepl %llux ndata %d\n", ep->rhrepl, cio->ndata);
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break;
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case Tbulk:
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case Tintr:
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@ -2211,63 +2208,46 @@ epclose(Ep *ep)
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ep->aux = nil;
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}
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static int
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static void
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portreset(Hci *hp, int port, int on)
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{
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Ctlr *ctlr;
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Ohci *ohci;
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if(on == 0)
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return 0;
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ctlr = hp->aux;
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eqlock(&ctlr->resetl);
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if(waserror()){
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qunlock(&ctlr->resetl);
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nexterror();
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}
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ilock(ctlr);
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ohci = ctlr->ohci;
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ohci->rhportsts[port - 1] = Spp;
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if((ohci->rhportsts[port - 1] & Ccs) == 0){
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iunlock(ctlr);
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error("port not connected");
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}
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ohci->rhportsts[port - 1] = Spr;
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while((ohci->rhportsts[port - 1] & Prsc) == 0){
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iunlock(ctlr);
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dprint("ohci: portreset, wait for reset complete\n");
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ilock(ctlr);
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}
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ohci->rhportsts[port - 1] = Prsc;
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if(on)
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ctlr->ohci->rhportsts[port - 1] = Spr;
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else if(ctlr->ohci->rhportsts[port - 1] & Prsc)
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ctlr->ohci->rhportsts[port - 1] = Prsc;
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iunlock(ctlr);
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poperror();
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qunlock(&ctlr->resetl);
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return 0;
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}
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static int
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static void
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portpower(Hci *hp, int port, int on)
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{
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Ctlr *ctlr;
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ctlr = hp->aux;
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ilock(ctlr);
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if(on)
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ctlr->ohci->rhportsts[port - 1] = Spp;
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else
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ctlr->ohci->rhportsts[port - 1] = Cpp;
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iunlock(ctlr);
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}
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static void
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portenable(Hci *hp, int port, int on)
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{
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Ctlr *ctlr;
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ctlr = hp->aux;
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dprint("ohci: %#p port %d enable=%d\n", ctlr->ohci, port, on);
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eqlock(&ctlr->resetl);
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if(waserror()){
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qunlock(&ctlr->resetl);
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nexterror();
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}
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ilock(ctlr);
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if(on)
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ctlr->ohci->rhportsts[port - 1] = Spe | Spp;
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ctlr->ohci->rhportsts[port - 1] = Spe;
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else
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ctlr->ohci->rhportsts[port - 1] = Cpe;
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iunlock(ctlr);
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tsleep(&up->sleep, return0, 0, Enabledelay);
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poperror();
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qunlock(&ctlr->resetl);
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return 0;
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}
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static int
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@ -2626,6 +2606,7 @@ reset(Hci *hp)
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hp->seprintep = seprintep;
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hp->portenable = portenable;
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hp->portreset = portreset;
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hp->portpower = portpower;
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hp->portstatus = portstatus;
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hp->shutdown = shutdown;
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hp->debug = usbdebug;
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@ -30,7 +30,6 @@ typedef struct Tdpool Tdpool;
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enum
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{
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Resetdelay = 100, /* delay after a controller reset (ms) */
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Enabledelay = 100, /* waiting for a port to enable */
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Abortdelay = 10, /* delay after cancelling Tds (ms) */
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Incr = 64, /* for Td and Qh pools */
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@ -2023,79 +2022,52 @@ seprintep(char *s, char *e, Ep *ep)
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return s;
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}
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static int
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static void
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portenable(Hci *hp, int port, int on)
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{
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int s;
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int ioport;
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Ctlr *ctlr;
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int ioport, s;
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ctlr = hp->aux;
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dprint("uhci: %#x port %d enable=%d\n", ctlr->port, port, on);
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ioport = PORT(port-1);
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eqlock(&ctlr->portlck);
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if(waserror()){
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qunlock(&ctlr->portlck);
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nexterror();
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}
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ilock(ctlr);
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s = INS(ioport);
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if(on)
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OUTS(ioport, s | PSenable);
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else
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OUTS(ioport, s & ~PSenable);
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microdelay(64);
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iunlock(ctlr);
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tsleep(&up->sleep, return0, 0, Enabledelay);
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dprint("uhci %#ux port %d enable=%d: sts %#x\n",
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ctlr->port, port, on, INS(ioport));
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qunlock(&ctlr->portlck);
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poperror();
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return 0;
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}
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static int
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static void
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portreset(Hci *hp, int port, int on)
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{
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int i, p;
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Ctlr *ctlr;
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int ioport;
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if(on == 0)
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return 0;
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ctlr = hp->aux;
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dprint("uhci: %#ux port %d reset\n", ctlr->port, port);
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p = PORT(port-1);
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ioport = PORT(port-1);
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eqlock(&ctlr->portlck);
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ilock(ctlr);
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OUTS(p, PSreset);
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delay(50);
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OUTS(p, INS(p) & ~PSreset);
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OUTS(p, INS(p) | PSenable);
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microdelay(64);
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for(i=0; i<1000 && (INS(p) & PSenable) == 0; i++)
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;
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OUTS(p, (INS(p) & ~PSreset)|PSenable);
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if(on)
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OUTS(ioport, PSreset);
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else
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OUTS(ioport, INS(ioport) & ~PSreset);
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iunlock(ctlr);
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dprint("uhci %#ux after port %d reset: sts %#x\n",
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ctlr->port, port, INS(p));
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return 0;
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qunlock(&ctlr->portlck);
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}
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static int
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portstatus(Hci *hp, int port)
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{
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int s;
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int r;
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int ioport;
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Ctlr *ctlr;
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int ioport, s, r;
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ctlr = hp->aux;
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ioport = PORT(port-1);
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eqlock(&ctlr->portlck);
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if(waserror()){
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iunlock(ctlr);
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qunlock(&ctlr->portlck);
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nexterror();
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}
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ilock(ctlr);
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s = INS(ioport);
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if(s & (PSstatuschg | PSchange)){
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@ -2104,7 +2076,6 @@ portstatus(Hci *hp, int port)
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}
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iunlock(ctlr);
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qunlock(&ctlr->portlck);
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poperror();
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/*
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* We must return status bits as a
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@ -93,6 +93,8 @@ enum
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/* Hub feature selectors */
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Rportenable = 1,
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Rportreset = 4,
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Rportpower = 8,
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Rbhportreset = 28,
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};
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@ -505,6 +507,9 @@ newdev(Hci *hp, Ep *hub, int port, int speed)
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d->ttport = d->ttt = d->mtt = 0;
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d->tthub = nil;
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d->rhrepl = -1;
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d->rhresetport = 0;
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if(hub != nil){
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d->hub = hub->dev;
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d->depth = d->hub->depth+1;
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@ -522,7 +527,7 @@ newdev(Hci *hp, Ep *hub, int port, int speed)
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}
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}
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d->rootport = rootport(hub, port);
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if(d->rootport == 0)
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if(d->rootport <= 0)
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error(Ebadport);
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} else {
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d->hub = nil;
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@ -1014,7 +1019,8 @@ usbopen(Chan *c, int omode)
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if(ep->dev->state == Ddetach)
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error(Edetach);
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ep->clrhalt = 0;
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ep->rhrepl = -1;
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if(ep->ttype == Tctl)
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ep->dev->rhrepl = -1;
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if(ep->ttype == Tiso)
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isotiming(ep);
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if(ep->load == 0 && ep->dev->speed != Superspeed)
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@ -1127,20 +1133,23 @@ static long
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rhubread(Ep *ep, void *a, long n)
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{
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uchar b[8];
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Udev *dev;
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if(ep->dev->depth >= 0 || ep->nb != 0 || n < 2 || ep->rhrepl == -1)
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dev = ep->dev;
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if(dev->depth >= 0 || ep->nb != 0 || n < 2 || dev->rhrepl == -1)
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return -1;
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b[0] = ep->rhrepl;
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b[1] = ep->rhrepl>>8;
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b[2] = ep->rhrepl>>16;
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b[3] = ep->rhrepl>>24;
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b[4] = ep->rhrepl>>32;
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b[5] = ep->rhrepl>>40;
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b[6] = ep->rhrepl>>48;
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b[7] = ep->rhrepl>>56;
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b[0] = dev->rhrepl;
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b[1] = dev->rhrepl>>8;
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b[2] = dev->rhrepl>>16;
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b[3] = dev->rhrepl>>24;
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b[4] = dev->rhrepl>>32;
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b[5] = dev->rhrepl>>40;
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b[6] = dev->rhrepl>>48;
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b[7] = dev->rhrepl>>56;
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ep->rhrepl = -1;
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dev->rhrepl = -1;
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if(n > sizeof(b))
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n = sizeof(b);
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@ -1157,33 +1166,70 @@ rhubwrite(Ep *ep, void *a, long n)
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int feature;
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int port;
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Hci *hp;
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Udev *dev;
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if(ep->dev->depth >= 0 || ep->nb != 0)
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hp = ep->hp;
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dev = ep->dev;
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if(dev->depth >= 0 || ep->nb != 0)
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return -1;
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if(n != Rsetuplen)
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error("root hub is a toy hub");
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ep->rhrepl = -1;
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s = a;
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if(s[Rtype] != (Rh2d|Rclass|Rother) && s[Rtype] != (Rd2h|Rclass|Rother))
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error("root hub is a toy hub");
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hp = ep->hp;
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/* terminate previous port reset */
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port = dev->rhresetport;
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if(port > 0){
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dev->rhresetport = 0;
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/* some controllers have to clear reset and set enable manually */
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if(hp->portreset != nil){
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(*hp->portreset)(hp, port, 0);
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tsleep(&up->sleep, return0, nil, 50);
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}
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if(hp->portenable != nil){
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(*hp->portenable)(hp, port, 1);
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tsleep(&up->sleep, return0, nil, 50);
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}
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}
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cmd = s[Rreq];
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feature = GET2(s+Rvalue);
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port = rootport(ep, GET2(s+Rindex));
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if(port == 0)
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if(port <= 0)
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error(Ebadport);
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dev->rhrepl = 0;
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switch(feature){
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case Rportpower:
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if(hp->portpower == nil)
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break;
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(*hp->portpower)(hp, port, cmd == Rsetfeature);
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break;
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case Rportenable:
|
||||
ep->rhrepl = (*hp->portenable)(hp, port, cmd == Rsetfeature);
|
||||
if(cmd != Rclearfeature || hp->portenable == nil)
|
||||
break;
|
||||
(*hp->portenable)(hp, port, 0);
|
||||
break;
|
||||
case Rbhportreset:
|
||||
if(cmd != Rsetfeature || hp->bhportreset == nil)
|
||||
break;
|
||||
(*hp->bhportreset)(hp, port, 1);
|
||||
break;
|
||||
case Rportreset:
|
||||
ep->rhrepl = (*hp->portreset)(hp, port, cmd == Rsetfeature);
|
||||
if(cmd != Rsetfeature || hp->portreset == nil)
|
||||
break;
|
||||
(*hp->portreset)(hp, port, 1);
|
||||
/* port reset in progress */
|
||||
dev->rhresetport = port;
|
||||
break;
|
||||
case Rgetstatus:
|
||||
ep->rhrepl = (*hp->portstatus)(hp, port);
|
||||
if(hp->portstatus == nil)
|
||||
break;
|
||||
dev->rhrepl = (*hp->portstatus)(hp, port);
|
||||
break;
|
||||
default:
|
||||
ep->rhrepl = 0;
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -117,9 +117,11 @@ struct Hciimpl
|
|||
long (*epwrite)(Ep*,void*,long); /* receive data for ep */
|
||||
char* (*seprintep)(char*,char*,Ep*); /* debug */
|
||||
void (*devclose)(Udev*); /* release the device */
|
||||
int (*portenable)(Hci*, int, int); /* enable/disable port */
|
||||
int (*portreset)(Hci*, int, int); /* set/clear port reset */
|
||||
int (*portstatus)(Hci*, int); /* get port status */
|
||||
void (*portenable)(Hci*, int, int); /* enable/disable root port */
|
||||
void (*portreset)(Hci*, int, int); /* set/clear root port reset */
|
||||
void (*bhportreset)(Hci*, int, int); /* set/clear warm root port reset (usb3) */
|
||||
void (*portpower)(Hci*, int, int); /* set/clear root port power state */
|
||||
int (*portstatus)(Hci*, int); /* get root port status */
|
||||
void (*shutdown)(Hci*); /* shutdown for reboot */
|
||||
void (*debug)(Hci*, int); /* set/clear debug flag */
|
||||
};
|
||||
|
|
@ -167,7 +169,6 @@ struct Ep
|
|||
int ttype; /* tranfer type */
|
||||
ulong load; /* in µs, for a transfer of maxpkt bytes */
|
||||
void* aux; /* for controller specific info */
|
||||
u64int rhrepl; /* fake root hub replies */
|
||||
int toggle[2]; /* saved toggles (while ep is not in use) */
|
||||
long pollival; /* poll interval ([µ]frames; intr/iso) */
|
||||
long hz; /* poll frequency (iso) */
|
||||
|
|
@ -204,6 +205,9 @@ struct Udev
|
|||
void *aux;
|
||||
|
||||
Ep *eps[Ndeveps]; /* end points for this device (cached) */
|
||||
|
||||
u64int rhrepl; /* fake root hub replies */
|
||||
int rhresetport; /* root port being reset */
|
||||
};
|
||||
|
||||
void addhcitype(char *type, int (*reset)(Hci*));
|
||||
|
|
|
|||
|
|
@ -51,7 +51,6 @@ enum
|
|||
Qclose,
|
||||
Qfree,
|
||||
|
||||
Enabledelay = 100, /* waiting for a port to enable */
|
||||
Abortdelay = 10, /* delay after cancelling Tds (ms) */
|
||||
|
||||
Incr = 64, /* for pools of Tds, Qhs, etc. */
|
||||
|
|
@ -1628,41 +1627,6 @@ interrupt(Ureg*, void* a)
|
|||
ehciintr(a);
|
||||
}
|
||||
|
||||
static int
|
||||
portenable(Hci *hp, int port, int on)
|
||||
{
|
||||
Ctlr *ctlr;
|
||||
Eopio *opio;
|
||||
int s;
|
||||
|
||||
ctlr = hp->aux;
|
||||
opio = ctlr->opio;
|
||||
s = opio->portsc[port-1];
|
||||
eqlock(&ctlr->portlck);
|
||||
if(waserror()){
|
||||
qunlock(&ctlr->portlck);
|
||||
nexterror();
|
||||
}
|
||||
dprint("ehci %#p port %d enable=%d; sts %#x\n",
|
||||
ctlr->capio, port, on, s);
|
||||
ilock(ctlr);
|
||||
if(s & (Psstatuschg | Pschange))
|
||||
opio->portsc[port-1] = s;
|
||||
if(on)
|
||||
opio->portsc[port-1] |= Psenable;
|
||||
else
|
||||
opio->portsc[port-1] &= ~Psenable;
|
||||
coherence();
|
||||
microdelay(64);
|
||||
iunlock(ctlr);
|
||||
tsleep(&up->sleep, return0, 0, Enabledelay);
|
||||
dprint("ehci %#p port %d enable=%d: sts %#lux\n",
|
||||
ctlr->capio, port, on, opio->portsc[port-1]);
|
||||
qunlock(&ctlr->portlck);
|
||||
poperror();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we detect during status that the port is low-speed or
|
||||
* during reset that it's full-speed, the device is not for
|
||||
|
|
@ -1678,67 +1642,53 @@ portlend(Ctlr *ctlr, int port, char *ss)
|
|||
ulong s;
|
||||
|
||||
opio = ctlr->opio;
|
||||
|
||||
dprint("ehci %#p port %d: %s speed device: no longer owned\n",
|
||||
ctlr->capio, port, ss);
|
||||
s = opio->portsc[port-1] & ~(Pschange|Psstatuschg);
|
||||
opio->portsc[port-1] = s | Psowner;
|
||||
coherence();
|
||||
}
|
||||
|
||||
static int
|
||||
portreset(Hci *hp, int port, int on)
|
||||
static void
|
||||
portenable(Hci *hp, int port, int on)
|
||||
{
|
||||
ulong *portscp;
|
||||
Eopio *opio;
|
||||
Ctlr *ctlr;
|
||||
int i;
|
||||
|
||||
if(on == 0)
|
||||
return 0;
|
||||
Eopio *opio;
|
||||
int s;
|
||||
|
||||
ctlr = hp->aux;
|
||||
opio = ctlr->opio;
|
||||
eqlock(&ctlr->portlck);
|
||||
if(waserror()){
|
||||
iunlock(ctlr);
|
||||
qunlock(&ctlr->portlck);
|
||||
nexterror();
|
||||
}
|
||||
portscp = &opio->portsc[port-1];
|
||||
dprint("ehci %#p port %d reset; sts %#lux\n", ctlr->capio, port, *portscp);
|
||||
ilock(ctlr);
|
||||
/* Shalted must be zero, else Psreset will stay set */
|
||||
if (opio->sts & Shalted)
|
||||
iprint("ehci %#p: halted yet trying to reset port\n",
|
||||
ctlr->capio);
|
||||
|
||||
*portscp = (*portscp & ~Psenable) | Psreset; /* initiate reset */
|
||||
/*
|
||||
* usb 2 spec: reset must finish within 20 ms.
|
||||
* linux says spec says it can take 50 ms. for hubs.
|
||||
*/
|
||||
delay(50);
|
||||
*portscp &= ~Psreset; /* terminate reset */
|
||||
|
||||
delay(10);
|
||||
for(i = 0; *portscp & Psreset && i < 10; i++)
|
||||
delay(10);
|
||||
|
||||
if (*portscp & Psreset)
|
||||
iprint("ehci %#p: port %d didn't reset; sts %#lux\n",
|
||||
ctlr->capio, port, *portscp);
|
||||
|
||||
delay(10); /* ehci spec: enable within 2 ms. */
|
||||
if((*portscp & Psenable) == 0)
|
||||
portlend(ctlr, port, "full");
|
||||
|
||||
s = opio->portsc[port-1];
|
||||
if(s & (Psstatuschg | Pschange))
|
||||
opio->portsc[port-1] = s;
|
||||
if(on){
|
||||
/* not enabled after reset? */
|
||||
if((s & Psenable) == 0)
|
||||
portlend(ctlr, port, "full");
|
||||
} else {
|
||||
opio->portsc[port-1] &= ~Psenable;
|
||||
}
|
||||
iunlock(ctlr);
|
||||
qunlock(&ctlr->portlck);
|
||||
}
|
||||
|
||||
static void
|
||||
portreset(Hci *hp, int port, int on)
|
||||
{
|
||||
Eopio *opio;
|
||||
Ctlr *ctlr;
|
||||
|
||||
ctlr = hp->aux;
|
||||
opio = ctlr->opio;
|
||||
eqlock(&ctlr->portlck);
|
||||
ilock(ctlr);
|
||||
if(on)
|
||||
opio->portsc[port-1] = (opio->portsc[port-1] & ~Psenable) | Psreset; /* initiate reset */
|
||||
else
|
||||
opio->portsc[port-1] &= ~Psreset; /* terminate reset */
|
||||
iunlock(ctlr);
|
||||
dprint("ehci %#p after port %d reset; sts %#lux\n",
|
||||
ctlr->capio, port, *portscp);
|
||||
qunlock(&ctlr->portlck);
|
||||
poperror();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -1751,18 +1701,10 @@ portstatus(Hci *hp, int port)
|
|||
ctlr = hp->aux;
|
||||
opio = ctlr->opio;
|
||||
eqlock(&ctlr->portlck);
|
||||
if(waserror()){
|
||||
iunlock(ctlr);
|
||||
qunlock(&ctlr->portlck);
|
||||
nexterror();
|
||||
}
|
||||
ilock(ctlr);
|
||||
s = opio->portsc[port-1];
|
||||
if(s & (Psstatuschg | Pschange)){
|
||||
if(s & (Psstatuschg | Pschange))
|
||||
opio->portsc[port-1] = s;
|
||||
coherence();
|
||||
ddprint("ehci %#p port %d status %#x\n", ctlr->capio, port, s);
|
||||
}
|
||||
/*
|
||||
* If the port is a low speed port we yield ownership now
|
||||
* to the [uo]hci companion controller and pretend it's not here.
|
||||
|
|
@ -1773,7 +1715,6 @@ portstatus(Hci *hp, int port)
|
|||
}
|
||||
iunlock(ctlr);
|
||||
qunlock(&ctlr->portlck);
|
||||
poperror();
|
||||
|
||||
/*
|
||||
* We must return status bits as a
|
||||
|
|
@ -1822,7 +1763,6 @@ seprintep(char *s, char *e, Ep *ep)
|
|||
case Tctl:
|
||||
cio = ep->aux;
|
||||
s = seprintio(s, e, cio, "c");
|
||||
s = seprint(s, e, "\trepl %llux ndata %d\n", ep->rhrepl, cio->ndata);
|
||||
break;
|
||||
case Tbulk:
|
||||
case Tintr:
|
||||
|
|
|
|||
|
|
@ -1785,26 +1785,61 @@ portstatus(Hci *hp, int port)
|
|||
|
||||
return ps;
|
||||
}
|
||||
|
||||
enum {
|
||||
RW1S = PR | WPR,
|
||||
RW1CS = PED | CSC | PEC | WRC | OCC | PRC | PLC | CEC,
|
||||
};
|
||||
|
||||
static int
|
||||
portenable(Hci*, int, int)
|
||||
static void
|
||||
portenable(Hci *hp, int port, int on)
|
||||
{
|
||||
return 0;
|
||||
Ctlr *ctlr = hp->aux;
|
||||
u32int *portsc;
|
||||
|
||||
if(on || ctlr->port == nil || needrecover(ctlr))
|
||||
return;
|
||||
portsc = &ctlr->port[port-1].reg[PORTSC];
|
||||
*portsc = (*portsc & ~(RW1CS|RW1S)) | PED;
|
||||
}
|
||||
|
||||
static int
|
||||
static void
|
||||
portreset(Hci *hp, int port, int on)
|
||||
{
|
||||
Ctlr *ctlr = hp->aux;
|
||||
u32int *portsc;
|
||||
|
||||
if(!on || ctlr->port == nil || needrecover(ctlr))
|
||||
return;
|
||||
portsc = &ctlr->port[port-1].reg[PORTSC];
|
||||
*portsc = (*portsc & ~(RW1CS|RW1S)) | PR;
|
||||
}
|
||||
|
||||
static void
|
||||
bhportreset(Hci *hp, int port, int on)
|
||||
{
|
||||
Ctlr *ctlr = hp->aux;
|
||||
u32int *portsc;
|
||||
|
||||
if(!on || ctlr->port == nil || needrecover(ctlr))
|
||||
return;
|
||||
portsc = &ctlr->port[port-1].reg[PORTSC];
|
||||
*portsc = (*portsc & ~(RW1CS|RW1S)) | WPR;
|
||||
}
|
||||
|
||||
static void
|
||||
portpower(Hci *hp, int port, int on)
|
||||
{
|
||||
Ctlr *ctlr = hp->aux;
|
||||
u32int *portsc;
|
||||
|
||||
if(ctlr->port == nil || needrecover(ctlr))
|
||||
return 0;
|
||||
|
||||
if(on){
|
||||
ctlr->port[port-1].reg[PORTSC] |= PR;
|
||||
tsleep(&up->sleep, return0, nil, 200);
|
||||
}
|
||||
return 0;
|
||||
return;
|
||||
portsc = &ctlr->port[port-1].reg[PORTSC];
|
||||
if(on)
|
||||
*portsc = (*portsc & ~(RW1CS|RW1S|PP)) | PP;
|
||||
else
|
||||
*portsc = (*portsc & ~(RW1CS|RW1S|PP));
|
||||
}
|
||||
|
||||
static u64int
|
||||
|
|
@ -1851,6 +1886,8 @@ xhcilinkage(Hci *hp, Xhci *ctlr)
|
|||
hp->devclose = devclose;
|
||||
hp->portenable = portenable;
|
||||
hp->portreset = portreset;
|
||||
hp->bhportreset = bhportreset;
|
||||
hp->portpower = portpower;
|
||||
hp->portstatus = portstatus;
|
||||
|
||||
hp->debug = setdebug;
|
||||
|
|
|
|||
Loading…
Reference in a new issue