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/sys/lib/acid: add power64

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This commit is contained in:
Jacob Moody 2023-11-04 20:52:35 +00:00
parent 4cdad07b98
commit 39c021fbc1
1 changed files with 142 additions and 0 deletions
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sys/lib/acid/power64 Normal file
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// power64
// incomplete until there are processes to debug
defn acidinit() // Called after all the init modules are loaded
{
bplist = {};
bpfmt = 'X';
srcpath = {
"./",
"/sys/src/libc/port/",
"/sys/src/libc/9sys/",
"/sys/src/libc/power64/"
};
srcfiles = {}; // list of loaded files
srctext = {}; // the text of the files
}
defn stk() // trace
{
_stk(*PC, *SP, linkreg(0), 0);
}
defn lstk() // trace with locals
{
_stk(*PC, *SP, linkreg(0), 1);
}
defn gpr() // print general purpose registers
{
print("R0 ", *R0, "\n");
print("SP ", *SP, "\n");
print("R2 ", *R2, "\n");
print("R3 ", *R3, "\n");
print("R4 ", *R4, "\n");
print("R5 ", *R5, "\n");
print("R6 ", *R6, "\n");
print("R7 ", *R7, "\n");
print("R8 ", *R8, "\n");
print("R9 ", *R9, "\n");
print("R10 ", *R10, "\n");
print("R11 ", *R11, "\n");
print("R12 ", *R12, "\n");
print("R13 ", *R13, "\n");
print("R14 ", *R14, "\n");
print("R15 ", *R15, "\n");
print("R16 ", *R16, "\n");
print("R17 ", *R17, "\n");
print("R18 ", *R18, "\n");
print("R19 ", *R19, "\n");
print("R20 ", *R20, "\n");
print("R21 ", *R21, "\n");
print("R22 ", *R22, "\n");
print("R23 ", *R23, "\n");
print("R24 ", *R24, "\n");
print("R25 ", *R25, "\n");
print("R26 ", *R26, "\n");
print("R27 ", *R27, "\n");
print("R28 ", *R28, "\n");
print("R29 ", *R29, "\n");
print("R30 ", *R30, "\n");
print("R31 ", *R31, "\n");
}
defn Fpr()
{
fpr();
}
defn fpr()
{
print("F0\t", *fmt(F0, 'G'), "\tF1\t", *fmt(F1, 'G'), "\n");
print("F2\t", *fmt(F2, 'G'), "\tF3\t", *fmt(F3, 'G'), "\n");
print("F4\t", *fmt(F4, 'G'), "\tF5\t", *fmt(F5, 'G'), "\n");
print("F6\t", *fmt(F6, 'G'), "\tF7\t", *fmt(F7, 'G'), "\n");
print("F8\t", *fmt(F8, 'G'), "\tF9\t", *fmt(F9, 'G'), "\n");
print("F10\t", *fmt(F10, 'G'), "\tF11\t", *fmt(F11, 'G'), "\n");
print("F12\t", *fmt(F12, 'G'), "\tF13\t", *fmt(F13, 'G'), "\n");
print("F14\t", *fmt(F14, 'G'), "\tF15\t", *fmt(F15, 'G'), "\n");
print("F16\t", *fmt(F16, 'G'), "\tF17\t", *fmt(F17, 'G'), "\n");
print("F18\t", *fmt(F18, 'G'), "\tF19\t", *fmt(F19, 'G'), "\n");
print("F20\t", *fmt(F20, 'G'), "\tF21\t", *fmt(F21, 'G'), "\n");
print("F22\t", *fmt(F22, 'G'), "\tF23\t", *fmt(F23, 'G'), "\n");
print("F24\t", *fmt(F24, 'G'), "\tF25\t", *fmt(F25, 'G'), "\n");
print("F26\t", *fmt(F26, 'G'), "\tF27\t", *fmt(F27, 'G'), "\n");
print("F28\t", *fmt(F28, 'G'), "\tF29\t", *fmt(F29, 'G'), "\n");
print("F30\t", *fmt(F30, 'G'), "\tF31\t", *fmt(F31, 'G'), "\n");
}
defn spr() // print special processor registers
{
local pc, link, cause;
pc = *PC;
print("PC\t", pc, " ", fmt(pc, 'a'), " ");
pfl(pc);
link = *R31;
print("SP\t", *SP, "\tLINK\t", link, " ", fmt(link, 'a'), " ");
pfl(link);
cause = *CAUSE;
print("SRR1\t", *SRR1, "\tCAUSE\t", cause, " ", reason(cause), "\n");
print("LR\t", *LR, "\tCR\t", *CR, "\n");
print("XER\t", *XER, "\tCTR\t", *CTR, "\n");
}
defn regs() // print all registers
{
spr();
gpr();
}
defn pstop(pid)
{
local l, pc;
pc = *PC;
print(pid,": ", reason(*CAUSE), "\t");
print(fmt(pc, 'a'), "\t", fmt(pc, 'i'), "\n");
if notes then {
if notes[0] != "sys: breakpoint" then {
print("Notes pending:\n");
l = notes;
while l do {
print("\t", head l, "\n");
l = tail l;
}
}
}
}
defn linkreg(addr)
{
return *LR;
}
print("/sys/lib/acid/power64");