mirror of
git://git.9front.org/plan9front/plan9front
synced 2025-01-12 11:10:06 +00:00
devether: make link status prints consistent
Provide ethersetlink() function for norifying about link status changes, which will do the printing that includes the controller number.
This commit is contained in:
parent
682e47137a
commit
5dde462f96
23 changed files with 113 additions and 112 deletions
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@ -1400,7 +1400,7 @@ linkdown(Ctlr *ctl)
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if(edev == nil || ctl->status == Disconnected)
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if(edev == nil || ctl->status == Disconnected)
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return;
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return;
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ctl->status = Disconnected;
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ctl->status = Disconnected;
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edev->link = 0;
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ethersetlink(edev, 0);
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/* send eof to aux/wpa */
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/* send eof to aux/wpa */
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for(i = 0; i < edev->nfile; i++){
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for(i = 0; i < edev->nfile; i++){
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f = edev->f[i];
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f = edev->f[i];
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@ -1550,7 +1550,7 @@ bcmevent(Ctlr *ctl, uchar *p, int len)
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break;
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break;
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case 16: /* E_LINK */
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case 16: /* E_LINK */
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if(flags&1){ /* link up */
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if(flags&1){ /* link up */
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ctl->edev->link = 1;
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ethersetlink(ctl->edev, 1);
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break;
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break;
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}
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}
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/* fall through */
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/* fall through */
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@ -1812,8 +1812,8 @@ wljoin(Ctlr *ctl, char *ssid, int chan)
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ctl->status = Connecting;
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ctl->status = Connecting;
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switch(waitjoin(ctl)){
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switch(waitjoin(ctl)){
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case 0:
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case 0:
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ctl->edev->link = 1;
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ctl->status = Connected;
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ctl->status = Connected;
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ethersetlink(ctl->edev, 1);
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break;
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break;
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case 3:
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case 3:
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ctl->status = Disconnected;
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ctl->status = Disconnected;
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@ -770,8 +770,7 @@ linkproc(void *arg)
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ethersetspeed(edev, phy->speed);
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ethersetspeed(edev, phy->speed);
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}
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}
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edev->link = link;
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ethersetlink(edev, link);
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// print("#l%d: link %d speed %d\n", edev->ctlrno, edev->link, edev->mbps);
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}
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}
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}
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}
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@ -111,7 +111,6 @@ ethproc(void *ved)
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{
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{
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Ether *edev;
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Ether *edev;
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Ctlr *c;
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Ctlr *c;
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char *sp, *dpl;
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u16int v;
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u16int v;
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edev = ved;
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edev = ved;
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@ -120,8 +119,7 @@ ethproc(void *ved)
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mdwrite(c, MDCTRL, AUTONEG);
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mdwrite(c, MDCTRL, AUTONEG);
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for(;;){
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for(;;){
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if((mdread(c, MDSTATUS) & LINK) == 0){
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if((mdread(c, MDSTATUS) & LINK) == 0){
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edev->link = 0;
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ethersetlink(edev, 0);
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print("eth: no link\n");
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while((mdread(c, MDSTATUS) & LINK) == 0)
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while((mdread(c, MDSTATUS) & LINK) == 0)
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tsleep(&up->sleep, return0, nil, Linkdelay);
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tsleep(&up->sleep, return0, nil, Linkdelay);
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}
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}
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@ -131,26 +129,19 @@ ethproc(void *ved)
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;
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;
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c->r[MAC_CONFIG] &= ~(1<<15);
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c->r[MAC_CONFIG] &= ~(1<<15);
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ethersetspeed(edev, 1000);
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ethersetspeed(edev, 1000);
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sp = "1000BASE-T";
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}else if((v & 0x20) != 0){
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}else if((v & 0x20) != 0){
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c->r[MAC_CONFIG] = c->r[MAC_CONFIG] | (1<<15|1<<14);
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c->r[MAC_CONFIG] = c->r[MAC_CONFIG] | (1<<15|1<<14);
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ethersetspeed(edev, 100);
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ethersetspeed(edev, 100);
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sp = "100BASE-TX";
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}else if((v & 0x10) != 0){
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}else if((v & 0x10) != 0){
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c->r[MAC_CONFIG] = c->r[MAC_CONFIG] & ~(1<<14) | 1<<15;
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c->r[MAC_CONFIG] = c->r[MAC_CONFIG] & ~(1<<14) | 1<<15;
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ethersetspeed(edev, 10);
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ethersetspeed(edev, 10);
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sp = "10BASE-T";
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}
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}else
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sp = "???";
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if((v & 0x08) != 0){
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if((v & 0x08) != 0){
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dpl = "full";
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c->r[MAC_CONFIG] |= 1<<11;
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c->r[MAC_CONFIG] |= 1<<11;
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}else{
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}else{
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dpl = "half";
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c->r[MAC_CONFIG] &= ~(1<<11);
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c->r[MAC_CONFIG] &= ~(1<<11);
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}
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}
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edev->link = 1;
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ethersetlink(edev, 1);
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print("eth: %s %s duplex link\n", sp, dpl);
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c->r[MAC_CONFIG] |= 1<<3 | 1<<2;
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c->r[MAC_CONFIG] |= 1<<3 | 1<<2;
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while((mdread(c, MDSTATUS) & LINK) != 0)
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while((mdread(c, MDSTATUS) & LINK) != 0)
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tsleep(&up->sleep, return0, nil, Linkdelay);
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tsleep(&up->sleep, return0, nil, Linkdelay);
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@ -519,8 +519,7 @@ linkproc(void *arg)
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wr(ctlr, ENET_RDAR, RDAR_ACTIVE);
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wr(ctlr, ENET_RDAR, RDAR_ACTIVE);
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}
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}
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edev->link = link;
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ethersetlink(edev, link);
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print("#l%d: link %d speed %d\n", edev->ctlrno, edev->link, edev->mbps);
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}
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}
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}
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}
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@ -866,9 +866,9 @@ interrupt(Ureg*, void *arg)
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* thus we note the link change here, and check for
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* thus we note the link change here, and check for
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* that and autonegotiation done below.
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* that and autonegotiation done below.
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*/
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*/
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if(irqe & IEphystschg) {
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if(irqe & IEphystschg){
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ether->link = (reg->ps0 & PS0linkup) != 0;
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ctlr->linkchg = 1;
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ctlr->linkchg = 1;
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ethersetlink(ether, reg->ps0 & PS0linkup);
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}
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}
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if(irqe & IEtxerrq(Qno))
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if(irqe & IEtxerrq(Qno))
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ether->oerrs++;
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ether->oerrs++;
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@ -895,8 +895,8 @@ interrupt(Ureg*, void *arg)
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if(ctlr->linkchg && (reg->ps1 & PS1an_done)) {
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if(ctlr->linkchg && (reg->ps1 & PS1an_done)) {
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handled++;
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handled++;
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ether->link = (reg->ps0 & PS0linkup) != 0;
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ctlr->linkchg = 0;
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ctlr->linkchg = 0;
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ethersetlink(ether, reg->ps0 & PS0linkup);
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}
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}
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ctlr->newintrs++;
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ctlr->newintrs++;
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@ -880,19 +880,21 @@ rtl8169link(Ether* edev)
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ctlr = edev->ctlr;
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ctlr = edev->ctlr;
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r = csr8r(ctlr, Phystatus);
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/*
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/*
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* Maybe the link changed - do we care very much?
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* Maybe the link changed - do we care very much?
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* Could stall transmits if no link, maybe?
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* Could stall transmits if no link, maybe?
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*/
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*/
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edev->link = (r & Linksts) != 0;
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r = csr8r(ctlr, Phystatus);
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if(edev->link){
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if(r & Linksts){
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if(r & Speed10)
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if(r & Speed10)
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ethersetspeed(edev, 10);
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ethersetspeed(edev, 10);
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else if(r & Speed100)
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else if(r & Speed100)
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ethersetspeed(edev, 100);
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ethersetspeed(edev, 100);
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else if(r & Speed1000)
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else if(r & Speed1000)
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ethersetspeed(edev, 1000);
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ethersetspeed(edev, 1000);
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ethersetlink(edev, 1);
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} else {
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ethersetlink(edev, 0);
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}
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}
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}
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}
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@ -508,7 +508,7 @@ struct Ctlr {
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uvlong port;
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uvlong port;
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Pcidev *pcidev;
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Pcidev *pcidev;
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Ctlr *next;
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Ctlr *next;
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int active;
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Ether *edev;
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int type;
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int type;
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u16int eeprom[0x40];
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u16int eeprom[0x40];
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@ -851,7 +851,7 @@ i82563cleanup(Ctlr *c)
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c->tb[tdh] = nil;
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c->tb[tdh] = nil;
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freeb(b);
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freeb(b);
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}else
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}else
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iprint("82563 tx underrun!\n");
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iprint("#l%d: %s: tx underrun!\n", c->edev->ctlrno, cname(c));
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c->tdba[tdh].status = 0;
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c->tdba[tdh].status = 0;
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}
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}
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@ -914,7 +914,7 @@ i82563replenish(Ctlr *ctlr)
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for(rdt = ctlr->rdt; NEXT(rdt, ctlr->nrd) != ctlr->rdh; rdt = NEXT(rdt, ctlr->nrd)){
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for(rdt = ctlr->rdt; NEXT(rdt, ctlr->nrd) != ctlr->rdh; rdt = NEXT(rdt, ctlr->nrd)){
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rd = &ctlr->rdba[rdt];
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rd = &ctlr->rdba[rdt];
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if(ctlr->rb[rdt] != nil){
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if(ctlr->rb[rdt] != nil){
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iprint("82563: tx overrun\n");
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iprint("#l%d: %s: tx overrun\n", ctlr->edev->ctlrno, cname(ctlr));
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break;
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break;
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}
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}
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i++;
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i++;
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@ -1097,7 +1097,7 @@ phyread(Ctlr *c, int phyno, int reg)
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microdelay(1);
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microdelay(1);
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}
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}
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if((phy & (MDIe|MDIready)) != MDIready){
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if((phy & (MDIe|MDIready)) != MDIready){
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print("%s: phy %d wedged %.8ux\n", cname(c), phyno, phy);
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print("#l%d: %s: phy %d wedged %.8ux\n", c->edev->ctlrno, cname(c), phyno, phy);
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return ~0;
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return ~0;
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}
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}
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return phy & 0xffff;
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return phy & 0xffff;
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@ -1143,18 +1143,18 @@ static uint
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phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
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phywrite(Ctlr *c, uint phyno, uint reg, ushort v)
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{
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{
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if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
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if(setpage(c, phyno, reg>>8, reg & 0xff) == ~0)
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panic("%s: bad phy reg %.4ux", cname(c), reg);
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panic("#l%d: %s: bad phy reg %.4ux", c->edev->ctlrno, cname(c), reg);
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return phywrite0(c, phyno, reg & 0xff, v);
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return phywrite0(c, phyno, reg & 0xff, v);
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}
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}
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static void
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static void
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phyerrata(Ether *e, Ctlr *c, uint phyno)
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phyerrata(Ctlr *c, uint phyno)
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{
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{
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if(e->mbps == 0){
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if(c->edev->mbps == 0){
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if(c->phyerrata == 0){
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if(c->phyerrata == 0){
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c->phyerrata++;
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c->phyerrata++;
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phywrite(c, phyno, Phyprst, Prst); /* try a port reset */
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phywrite(c, phyno, Phyprst, Prst); /* try a port reset */
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print("%s: phy port reset\n", cname(c));
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print("#l%d: %s: phy port reset\n", c->edev->ctlrno, cname(c));
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}
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}
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}else
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}else
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c->phyerrata = 0;
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c->phyerrata = 0;
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@ -1174,10 +1174,11 @@ phyprobe(Ctlr *c, uint mask)
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phy |= phyread(c, phyno, Phyid2) >> 10;
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phy |= phyread(c, phyno, Phyid2) >> 10;
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if(phy == 0xFFFFF || phy == 0)
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if(phy == 0xFFFFF || phy == 0)
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continue;
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continue;
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print("%s: phy%d oui %#ux\n", cname(c), phyno, phy);
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print("#l%d: %s: phy%d oui %#ux\n", c->edev->ctlrno, cname(c),
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phyno, phy);
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return phyno;
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return phyno;
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}
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}
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print("%s: no phy\n", cname(c));
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print("#l%d: %s: no phy\n", c->edev->ctlrno, cname(c));
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return ~0;
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return ~0;
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}
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}
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@ -1221,11 +1222,13 @@ phyl79proc(void *v)
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break;
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break;
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}
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}
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i = (phy>>8) & 3;
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i = (phy>>8) & 3;
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e->link = i != 3 && (phy & Link) != 0;
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if(i != 3 && (phy & Link) != 0){
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if(e->link)
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ethersetspeed(e, speedtab[i]);
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ethersetspeed(e, speedtab[i]);
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else
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ethersetlink(e, 1);
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}else{
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ethersetlink(e, 0);
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i = 3;
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i = 3;
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}
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c->speeds[i]++;
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c->speeds[i]++;
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lsleep(c, Lsc);
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lsleep(c, Lsc);
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}
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}
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@ -1278,14 +1281,16 @@ phylproc(void *v)
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if(a)
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if(a)
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phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
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phywrite(c, phyno, Phyctl, phyread(c, phyno, Phyctl) | Ran | Ean);
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next:
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next:
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e->link = (phy & Rtlink) != 0;
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if(phy & Rtlink){
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if(e->link)
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ethersetspeed(e, speedtab[i]);
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ethersetspeed(e, speedtab[i]);
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else
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ethersetlink(e, 1);
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}else{
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ethersetlink(e, 0);
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i = 3;
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i = 3;
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}
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c->speeds[i]++;
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c->speeds[i]++;
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if(c->type == i82563)
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if(c->type == i82563)
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phyerrata(e, c, phyno);
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phyerrata(c, phyno);
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lsleep(c, Lsc);
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lsleep(c, Lsc);
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}
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}
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}
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}
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@ -1306,13 +1311,16 @@ pcslproc(void *v)
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csr32w(c, Connsw, Enrgirq);
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csr32w(c, Connsw, Enrgirq);
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for(;;){
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for(;;){
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phy = csr32r(c, Pcsstat);
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phy = csr32r(c, Pcsstat);
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e->link = phy & Linkok;
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if(phy & Linkok){
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i = 3;
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if(e->link){
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i = (phy & 6) >> 1;
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i = (phy & 6) >> 1;
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ethersetspeed(e, speedtab[i]);
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ethersetspeed(e, speedtab[i]);
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}else if(phy & Anbad)
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ethersetlink(e, 1);
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csr32w(c, Pcsctl, csr32r(c, Pcsctl) | Pan | Prestart);
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}else {
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ethersetlink(e, 0);
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if(phy & Anbad)
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csr32w(c, Pcsctl, csr32r(c, Pcsctl) | Pan | Prestart);
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i = 3;
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}
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c->speeds[i]++;
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c->speeds[i]++;
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lsleep(c, Lsc | Omed);
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lsleep(c, Lsc | Omed);
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}
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}
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@ -1333,12 +1341,13 @@ serdeslproc(void *v)
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rx = csr32r(c, Rxcw);
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rx = csr32r(c, Rxcw);
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tx = csr32r(c, Txcw);
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tx = csr32r(c, Txcw);
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USED(tx);
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USED(tx);
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e->link = (rx & 1<<31) != 0;
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if(rx & 1<<31){ /*(csr32r(c, Status) & Lu*/
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// e->link = (csr32r(c, Status) & Lu) != 0;
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i = 3;
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if(e->link){
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i = 2;
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i = 2;
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ethersetspeed(e, speedtab[i]);
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ethersetspeed(e, speedtab[i]);
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ethersetlink(e, 1);
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} else {
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ethersetlink(e, 0);
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i = 3;
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}
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}
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c->speeds[i]++;
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c->speeds[i]++;
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lsleep(c, Lsc);
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lsleep(c, Lsc);
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@ -1538,7 +1547,7 @@ eeread(Ctlr *ctlr, int adr)
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while ((csr32r(ctlr, Eerd) & EEdone) == 0 && timeout--)
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while ((csr32r(ctlr, Eerd) & EEdone) == 0 && timeout--)
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microdelay(5);
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microdelay(5);
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if (timeout < 0) {
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if (timeout < 0) {
|
||||||
print("%s: eeread timeout\n", cname(ctlr));
|
print("#l%d: %s: eeread timeout\n", ctlr->edev->ctlrno, cname(ctlr));
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
return (csr32r(ctlr, Eerd) >> 16) & 0xffff;
|
return (csr32r(ctlr, Eerd) >> 16) & 0xffff;
|
||||||
|
@ -1589,7 +1598,7 @@ done:
|
||||||
while((f->reg[Fsts] & Fdone) == 0 && timeout--)
|
while((f->reg[Fsts] & Fdone) == 0 && timeout--)
|
||||||
microdelay(5);
|
microdelay(5);
|
||||||
if(timeout < 0){
|
if(timeout < 0){
|
||||||
print("%s: fread timeout\n", cname(c));
|
print("#l%d: %s: fread timeout\n", c->edev->ctlrno, cname(c));
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
if(f->reg[Fsts] & (Fcerr|Ael))
|
if(f->reg[Fsts] & (Fcerr|Ael))
|
||||||
|
@ -1626,7 +1635,7 @@ done:
|
||||||
while((f->reg32[Fsts/2] & Fdone) == 0 && timeout--)
|
while((f->reg32[Fsts/2] & Fdone) == 0 && timeout--)
|
||||||
microdelay(5);
|
microdelay(5);
|
||||||
if(timeout < 0){
|
if(timeout < 0){
|
||||||
print("%s: fread timeout\n", cname(c));
|
print("#l%d: %s: fread timeout\n", c->edev->ctlrno, cname(c));
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
if(f->reg32[Fsts/2] & (Fcerr|Ael))
|
if(f->reg32[Fsts/2] & (Fcerr|Ael))
|
||||||
|
@ -1777,7 +1786,7 @@ i82563reset(Ctlr *ctlr)
|
||||||
r = eeload(ctlr);
|
r = eeload(ctlr);
|
||||||
|
|
||||||
if(r != 0 && r != 0xbaba){
|
if(r != 0 && r != 0xbaba){
|
||||||
print("%s: bad eeprom checksum - %#.4ux", cname(ctlr), r);
|
print("#l%d: %s: bad eeprom checksum - %#.4ux", ctlr->edev->ctlrno, cname(ctlr), r);
|
||||||
if(flag & Fbadcsum)
|
if(flag & Fbadcsum)
|
||||||
print("; ignored\n");
|
print("; ignored\n");
|
||||||
else {
|
else {
|
||||||
|
@ -2101,12 +2110,12 @@ pnp(Ether *edev, int type)
|
||||||
for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
|
for(ctlr = i82563ctlrhead; ; ctlr = ctlr->next){
|
||||||
if(ctlr == nil)
|
if(ctlr == nil)
|
||||||
return -1;
|
return -1;
|
||||||
if(ctlr->active)
|
if(ctlr->edev != nil)
|
||||||
continue;
|
continue;
|
||||||
if(type != -1 && ctlr->type != type)
|
if(type != -1 && ctlr->type != type)
|
||||||
continue;
|
continue;
|
||||||
if(edev->port == 0 || edev->port == ctlr->port){
|
if(edev->port == 0 || edev->port == ctlr->port){
|
||||||
ctlr->active = 1;
|
ctlr->edev = edev;
|
||||||
memmove(ctlr->ra, edev->ea, Eaddrlen);
|
memmove(ctlr->ra, edev->ea, Eaddrlen);
|
||||||
if(setup(ctlr) == 0)
|
if(setup(ctlr) == 0)
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -384,11 +384,13 @@ lproc(void *v)
|
||||||
;
|
;
|
||||||
for (;;) {
|
for (;;) {
|
||||||
r = c->reg[Links];
|
r = c->reg[Links];
|
||||||
e->link = (r & Lnkup) != 0;
|
if(r & Lnkup){
|
||||||
i = 0;
|
|
||||||
if(e->link){
|
|
||||||
i = 1 + ((r & Lnkspd) != 0);
|
i = 1 + ((r & Lnkspd) != 0);
|
||||||
ethersetspeed(e, speedtab[i]);
|
ethersetspeed(e, speedtab[i]);
|
||||||
|
ethersetlink(e, 1);
|
||||||
|
} else {
|
||||||
|
ethersetlink(e, 0);
|
||||||
|
i = 0;
|
||||||
}
|
}
|
||||||
c->speeds[i]++;
|
c->speeds[i]++;
|
||||||
c->lim = 0;
|
c->lim = 0;
|
||||||
|
|
|
@ -333,15 +333,14 @@ checklink(Ether *edev)
|
||||||
ulong i;
|
ulong i;
|
||||||
int mbps;
|
int mbps;
|
||||||
|
|
||||||
|
mbps = 0;
|
||||||
ctlr = edev->ctlr;
|
ctlr = edev->ctlr;
|
||||||
miir(ctlr, PhyStatus); /* dummy read necessary */
|
miir(ctlr, PhyStatus); /* dummy read necessary */
|
||||||
if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
|
if(!(miir(ctlr, PhyStatus) & PhyLinkStatus)) {
|
||||||
edev->link = 0;
|
|
||||||
ctlr->duplex = 1;
|
ctlr->duplex = 1;
|
||||||
print("bcm: no link\n");
|
ethersetlink(edev, 0);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
edev->link = 1;
|
|
||||||
while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
|
while((miir(ctlr, PhyStatus) & PhyAutoNegComplete) == 0);
|
||||||
i = miir(ctlr, PhyGbitStatus);
|
i = miir(ctlr, PhyGbitStatus);
|
||||||
if(i & (Phy1000FD | Phy1000HD)) {
|
if(i & (Phy1000FD | Phy1000HD)) {
|
||||||
|
@ -354,13 +353,12 @@ checklink(Ether *edev)
|
||||||
mbps = 10;
|
mbps = 10;
|
||||||
ctlr->duplex = (i & Phy10FD) != 0;
|
ctlr->duplex = (i & Phy10FD) != 0;
|
||||||
} else {
|
} else {
|
||||||
edev->link = 0;
|
|
||||||
ctlr->duplex = 1;
|
ctlr->duplex = 1;
|
||||||
print("bcm: link partner supports neither 10/100/1000 Mbps\n");
|
ethersetlink(edev, 0);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
print("bcm: %d Mbps link, %s duplex\n", mbps, ctlr->duplex ? "full" : "half");
|
|
||||||
ethersetspeed(edev, mbps);
|
ethersetspeed(edev, mbps);
|
||||||
|
ethersetlink(edev, 1);
|
||||||
out:
|
out:
|
||||||
if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
|
if(ctlr->duplex) csr32(ctlr, MACMode) &= ~MACHalfDuplex;
|
||||||
else csr32(ctlr, MACMode) |= MACHalfDuplex;
|
else csr32(ctlr, MACMode) |= MACHalfDuplex;
|
||||||
|
|
|
@ -2118,6 +2118,8 @@ etherelnk3reset(Ether* ether)
|
||||||
|
|
||||||
intrenable(ether->irq, interrupt, ether, ether->tbdf, ether->name);
|
intrenable(ether->irq, interrupt, ether, ether->tbdf, ether->name);
|
||||||
|
|
||||||
|
ether->link = ether->mbps != 0;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -583,17 +583,12 @@ ga620event(Ether *edev, int eci, int epi)
|
||||||
case 1:
|
case 1:
|
||||||
ethersetspeed(edev, 1000);
|
ethersetspeed(edev, 1000);
|
||||||
break;
|
break;
|
||||||
case 2:
|
|
||||||
print("#l%d: link down\n", edev->ctlrno);
|
|
||||||
break;
|
|
||||||
case 3:
|
case 3:
|
||||||
/* it's 10 or 100 */
|
/* it's 10 or 100 */
|
||||||
ethersetspeed(edev, 100);
|
ethersetspeed(edev, 100);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (code != 2)
|
ethersetlink(edev, code != 2);
|
||||||
print("#l%d: %dMbps link up\n",
|
|
||||||
edev->ctlrno, edev->mbps);
|
|
||||||
break;
|
break;
|
||||||
case 0x07: /* event error */
|
case 0x07: /* event error */
|
||||||
default:
|
default:
|
||||||
|
|
|
@ -1242,13 +1242,8 @@ checkstats(Ether *e, Ctlr *c, Stats *s)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
i = gbit32(s->linkstat);
|
i = gbit32(s->linkstat);
|
||||||
if(c->linkstat != i){
|
if(c->linkstat != i)
|
||||||
e->link = i;
|
ethersetlink(e, c->linkstat = i);
|
||||||
if(c->linkstat = i)
|
|
||||||
dprint("m10g: link up\n");
|
|
||||||
else
|
|
||||||
dprint("m10g: link down\n");
|
|
||||||
}
|
|
||||||
i = gbit32(s->nrdma);
|
i = gbit32(s->nrdma);
|
||||||
if(i != c->nrdma){
|
if(i != c->nrdma){
|
||||||
dprint("m10g: rdma timeout %ld\n", i);
|
dprint("m10g: rdma timeout %ld\n", i);
|
||||||
|
|
|
@ -713,9 +713,8 @@ vgbeinterrupt(Ureg *, void* arg)
|
||||||
print("vgbe: irq: PHY interrupt\n");
|
print("vgbe: irq: PHY interrupt\n");
|
||||||
|
|
||||||
if(status & Isr_LinkStatus){
|
if(status & Isr_LinkStatus){
|
||||||
edev->link = (riob(ctlr, PhySts0) & PhySts_Link) ? 1 : 0;
|
ethersetlink(edev, riob(ctlr, PhySts0) & PhySts_Link);
|
||||||
vgbemiip(ctlr, 1);
|
vgbemiip(ctlr, 1);
|
||||||
print("vgbe: irq: link status change\n");
|
|
||||||
}
|
}
|
||||||
if(status & Isr_RxNoDesc)
|
if(status & Isr_RxNoDesc)
|
||||||
print("vgbe: irq: ran out of Rx descriptors\n");
|
print("vgbe: irq: ran out of Rx descriptors\n");
|
||||||
|
|
|
@ -346,11 +346,13 @@ lproc(void *v)
|
||||||
;
|
;
|
||||||
for (;;) {
|
for (;;) {
|
||||||
r = c->reg[Links];
|
r = c->reg[Links];
|
||||||
e->link = (r & Lnkup) != 0;
|
if(r & Lnkup){
|
||||||
i = 0;
|
|
||||||
if(e->link){
|
|
||||||
i = 1 + ((r & Lnkspd) != 0);
|
i = 1 + ((r & Lnkspd) != 0);
|
||||||
ethersetspeed(e, speedtab[i]);
|
ethersetspeed(e, speedtab[i]);
|
||||||
|
ethersetlink(e, 1);
|
||||||
|
} else {
|
||||||
|
ethersetlink(e, 0);
|
||||||
|
i = 0;
|
||||||
}
|
}
|
||||||
c->speeds[i]++;
|
c->speeds[i]++;
|
||||||
c->lim = 0;
|
c->lim = 0;
|
||||||
|
|
|
@ -1365,10 +1365,12 @@ link(Ether *e)
|
||||||
i = phyread(c, Phyint);
|
i = phyread(c, Phyint);
|
||||||
s = phyread(c, Phylstat);
|
s = phyread(c, Phylstat);
|
||||||
dprint("#l%d: yuk: link %.8ux %.8ux\n", e->ctlrno, i, s);
|
dprint("#l%d: yuk: link %.8ux %.8ux\n", e->ctlrno, i, s);
|
||||||
e->link = (s & Plink) != 0;
|
if(s & Plink){
|
||||||
if(e->link)
|
|
||||||
ethersetspeed(e, (c->feat&Ffiber)? 1000: spdtab[(s & Physpd) >> 14]);
|
ethersetspeed(e, (c->feat&Ffiber)? 1000: spdtab[(s & Physpd) >> 14]);
|
||||||
dprint("#l%d: yuk: link %d spd %d\n", e->ctlrno, e->link, e->mbps);
|
ethersetlink(e, 1);
|
||||||
|
} else {
|
||||||
|
ethersetlink(e, 0);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
|
|
@ -475,6 +475,17 @@ ethersetspeed(Ether *ether, int mbps)
|
||||||
return;
|
return;
|
||||||
netifsetlimit(ether, etherqueuesize(ether));
|
netifsetlimit(ether, etherqueuesize(ether));
|
||||||
qsetlimit(ether->oq, ether->limit);
|
qsetlimit(ether->oq, ether->limit);
|
||||||
|
print("#l%d: %s: speed %dMbps\n", ether->ctlrno, ether->type, mbps);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
ethersetlink(Ether *ether, int link)
|
||||||
|
{
|
||||||
|
link = !!link;
|
||||||
|
if(!!ether->link == link)
|
||||||
|
return;
|
||||||
|
ether->link = link;
|
||||||
|
print("#l%d: %s: link %s\n", ether->ctlrno, ether->type, link? "up": "down");
|
||||||
}
|
}
|
||||||
|
|
||||||
static void netconsole(int);
|
static void netconsole(int);
|
||||||
|
|
|
@ -52,6 +52,7 @@ struct Ether {
|
||||||
};
|
};
|
||||||
|
|
||||||
extern void ethersetspeed(Ether*, int);
|
extern void ethersetspeed(Ether*, int);
|
||||||
|
extern void ethersetlink(Ether*, int);
|
||||||
extern void etheriq(Ether*, Block*);
|
extern void etheriq(Ether*, Block*);
|
||||||
extern void addethercard(char*, int(*)(Ether*));
|
extern void addethercard(char*, int(*)(Ether*));
|
||||||
extern ulong ethercrc(uchar*, int);
|
extern ulong ethercrc(uchar*, int);
|
||||||
|
|
|
@ -54,6 +54,7 @@ reset(Ether* ether)
|
||||||
{
|
{
|
||||||
if(ether->type==nil)
|
if(ether->type==nil)
|
||||||
return -1;
|
return -1;
|
||||||
|
ether->link = 0;
|
||||||
ether->mbps = 1000;
|
ether->mbps = 1000;
|
||||||
ether->attach = attach;
|
ether->attach = attach;
|
||||||
ether->multicast = multicast;
|
ether->multicast = multicast;
|
||||||
|
|
|
@ -780,7 +780,6 @@ reset(Ether* edev)
|
||||||
edev->multicast = multicast;
|
edev->multicast = multicast;
|
||||||
edev->promiscuous = promiscuous;
|
edev->promiscuous = promiscuous;
|
||||||
|
|
||||||
|
|
||||||
pcisetbme(ctlr->pcidev);
|
pcisetbme(ctlr->pcidev);
|
||||||
intrenable(edev->irq, interrupt, edev, edev->tbdf, edev->name);
|
intrenable(edev->irq, interrupt, edev, edev->tbdf, edev->name);
|
||||||
|
|
||||||
|
|
|
@ -815,9 +815,13 @@ Scan:
|
||||||
/* maintain access point */
|
/* maintain access point */
|
||||||
tmout = 0;
|
tmout = 0;
|
||||||
while((wn = wifi->bss) != nil){
|
while((wn = wifi->bss) != nil){
|
||||||
ether->link = (wn->status == Sassoc) || (wn->status == Sblocked);
|
if(wn->status == Sassoc || wn->status == Sblocked){
|
||||||
if(ether->link && (rate = wn->actrate) != nil)
|
if((rate = wn->actrate) != nil)
|
||||||
ethersetspeed(ether, ((*rate & 0x7f)+3)/4);
|
ethersetspeed(ether, ((*rate & 0x7f)+3)/4);
|
||||||
|
ethersetlink(ether, 1);
|
||||||
|
} else {
|
||||||
|
ethersetlink(ether, 0);
|
||||||
|
}
|
||||||
now = MACHP(0)->ticks;
|
now = MACHP(0)->ticks;
|
||||||
if(wn->status != Sneedauth && TK2SEC(now - wn->lastseen) > 20 || goodbss(wifi, wn) == 0){
|
if(wn->status != Sneedauth && TK2SEC(now - wn->lastseen) > 20 || goodbss(wifi, wn) == 0){
|
||||||
wifideauth(wifi, wn);
|
wifideauth(wifi, wn);
|
||||||
|
|
|
@ -867,10 +867,11 @@ fccltimer(Ureg*, Timer *t)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
if(phy->link == 0){
|
if(phy->link == 0){
|
||||||
print("link lost\n");
|
ethersetlink(ether, 0);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
ethersetspeed(ether, phy->speed);
|
ethersetspeed(ether, phy->speed);
|
||||||
|
ethersetlink(ether, 1);
|
||||||
|
|
||||||
if(phy->fd != ctlr->duplex)
|
if(phy->fd != ctlr->duplex)
|
||||||
print("set duplex\n");
|
print("set duplex\n");
|
||||||
|
|
|
@ -1280,24 +1280,22 @@ rtl8169link(Ether* edev)
|
||||||
ctlr = edev->ctlr;
|
ctlr = edev->ctlr;
|
||||||
|
|
||||||
if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
|
if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
|
||||||
if (edev->link) {
|
if(edev->link) {
|
||||||
edev->link = 0;
|
|
||||||
csr8w(ctlr, Cr, Re);
|
csr8w(ctlr, Cr, Re);
|
||||||
iprint("#l%d: link down\n", edev->ctlrno);
|
ethersetlink(edev, 0);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
if(edev->link == 0) {
|
|
||||||
edev->link = 1;
|
|
||||||
csr8w(ctlr, Cr, Te|Re);
|
|
||||||
iprint("#l%d: link up\n", edev->ctlrno);
|
|
||||||
}
|
|
||||||
if(r & Speed10)
|
if(r & Speed10)
|
||||||
ethersetspeed(edev, 10);
|
ethersetspeed(edev, 10);
|
||||||
else if(r & Speed100)
|
else if(r & Speed100)
|
||||||
ethersetspeed(edev, 100);
|
ethersetspeed(edev, 100);
|
||||||
else if(r & Speed1000)
|
else if(r & Speed1000)
|
||||||
ethersetspeed(edev, 1000);
|
ethersetspeed(edev, 1000);
|
||||||
|
if(edev->link == 0) {
|
||||||
|
csr8w(ctlr, Cr, Te|Re);
|
||||||
|
ethersetlink(edev, 1);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
|
|
|
@ -141,7 +141,6 @@ ethproc(void *ved)
|
||||||
{
|
{
|
||||||
Ether *edev;
|
Ether *edev;
|
||||||
Ctlr *c;
|
Ctlr *c;
|
||||||
char *sp, *dpl;
|
|
||||||
u16int v;
|
u16int v;
|
||||||
|
|
||||||
edev = ved;
|
edev = ved;
|
||||||
|
@ -149,40 +148,32 @@ ethproc(void *ved)
|
||||||
mdwrite(c, MDCTRL, AUTONEG);
|
mdwrite(c, MDCTRL, AUTONEG);
|
||||||
for(;;){
|
for(;;){
|
||||||
if((mdread(c, MDSTATUS) & LINK) == 0){
|
if((mdread(c, MDSTATUS) & LINK) == 0){
|
||||||
edev->link = 0;
|
ethersetlink(edev, 0);
|
||||||
print("eth: no link\n");
|
|
||||||
while((mdread(c, MDSTATUS) & LINK) == 0)
|
while((mdread(c, MDSTATUS) & LINK) == 0)
|
||||||
tsleep(&up->sleep, return0, nil, Linkdelay);
|
tsleep(&up->sleep, return0, nil, Linkdelay);
|
||||||
}
|
}
|
||||||
v = mdread(c, MDPHYCTRL);
|
v = mdread(c, MDPHYCTRL);
|
||||||
if((v & 0x40) != 0){
|
if((v & 0x40) != 0){
|
||||||
sp = "1000BASE-T";
|
|
||||||
while((mdread(c, MDGSTATUS) & RECVOK) != RECVOK)
|
while((mdread(c, MDGSTATUS) & RECVOK) != RECVOK)
|
||||||
;
|
;
|
||||||
c->r[NET_CFG] |= GIGE_EN;
|
c->r[NET_CFG] |= GIGE_EN;
|
||||||
slcr[GEM0_CLK_CTRL] = 1 << 20 | 8 << 8 | 1;
|
slcr[GEM0_CLK_CTRL] = 1 << 20 | 8 << 8 | 1;
|
||||||
ethersetspeed(edev, 1000);
|
ethersetspeed(edev, 1000);
|
||||||
}else if((v & 0x20) != 0){
|
}else if((v & 0x20) != 0){
|
||||||
sp = "100BASE-TX";
|
|
||||||
c->r[NET_CFG] = c->r[NET_CFG] & ~GIGE_EN | SPEED;
|
c->r[NET_CFG] = c->r[NET_CFG] & ~GIGE_EN | SPEED;
|
||||||
slcr[GEM0_CLK_CTRL] = 5 << 20 | 8 << 8 | 1;
|
slcr[GEM0_CLK_CTRL] = 5 << 20 | 8 << 8 | 1;
|
||||||
ethersetspeed(edev, 100);
|
ethersetspeed(edev, 100);
|
||||||
}else if((v & 0x10) != 0){
|
}else if((v & 0x10) != 0){
|
||||||
sp = "10BASE-T";
|
|
||||||
c->r[NET_CFG] = c->r[NET_CFG] & ~(GIGE_EN | SPEED);
|
c->r[NET_CFG] = c->r[NET_CFG] & ~(GIGE_EN | SPEED);
|
||||||
slcr[GEM0_CLK_CTRL] = 20 << 20 | 20 << 8 | 1;
|
slcr[GEM0_CLK_CTRL] = 20 << 20 | 20 << 8 | 1;
|
||||||
ethersetspeed(edev, 10);
|
ethersetspeed(edev, 10);
|
||||||
}else
|
}
|
||||||
sp = "???";
|
|
||||||
if((v & 0x08) != 0){
|
if((v & 0x08) != 0){
|
||||||
dpl = "full";
|
|
||||||
c->r[NET_CFG] |= FDEN;
|
c->r[NET_CFG] |= FDEN;
|
||||||
}else{
|
}else{
|
||||||
dpl = "half";
|
|
||||||
c->r[NET_CFG] &= ~FDEN;
|
c->r[NET_CFG] &= ~FDEN;
|
||||||
}
|
}
|
||||||
edev->link = 1;
|
ethersetlink(edev, 1);
|
||||||
print("eth: %s %s duplex link\n", sp, dpl);
|
|
||||||
while((mdread(c, MDSTATUS) & LINK) != 0)
|
while((mdread(c, MDSTATUS) & LINK) != 0)
|
||||||
tsleep(&up->sleep, return0, nil, Linkdelay);
|
tsleep(&up->sleep, return0, nil, Linkdelay);
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue