cirno/plan9front
1
0
Fork 0
mirror of git://git.9front.org/plan9front/plan9front synced 2025-01-12 11:10:06 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

mt7688/uarti8250.c; fixed interrupts

Browse source
This commit is contained in:
adventuresin9 2024-01-02 04:54:30 +00:00
parent f62e54b13d
commit 5de941cbcf
1 changed files with 6 additions and 17 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
sys/src/9/mt7688/uarti8250.c
View file

@ -20,8 +20,7 @@ enum { /* registers */
Lsr = 5, /* Line Status */ Lsr = 5, /* Line Status */
Msr = 6, /* Modem Status */ Msr = 6, /* Modem Status */
Scr = 7, /* Scratch Pad */ Scr = 7, /* Scratch Pad */
// Mdr = 8, /* Mode Def'n (omap rw) missing on mt7688*/ // Mdr = 8, /* Mode Def'n (missing on mt7688)*/
// Usr = 31, /* Uart Status Register; missing in omap? */
Dll = 0, /* Divisor Latch LSB */ Dll = 0, /* Divisor Latch LSB */
Dlm = 1, /* Divisor Latch MSB */ Dlm = 1, /* Divisor Latch MSB */
}; };
@ -52,7 +51,7 @@ enum { /* Fcr */
FIFOena = 0x01, /* FIFO enable */ FIFOena = 0x01, /* FIFO enable */
FIFOrclr = 0x02, /* clear Rx FIFO */ FIFOrclr = 0x02, /* clear Rx FIFO */
FIFOtclr = 0x04, /* clear Tx FIFO */ FIFOtclr = 0x04, /* clear Tx FIFO */
// FIFOdma = 0x08, FIFOdma = 0x08,
FIFO1 = 0x00, /* Rx FIFO trigger level 1 byte */ FIFO1 = 0x00, /* Rx FIFO trigger level 1 byte */
FIFO4 = 0x40, /* 4 bytes */ FIFO4 = 0x40, /* 4 bytes */
FIFO8 = 0x80, /* 8 bytes */ FIFO8 = 0x80, /* 8 bytes */
@ -76,8 +75,8 @@ enum { /* Lcr */
enum { /* Mcr */ enum { /* Mcr */
Dtr = 0x01, /* Data Terminal Ready */ Dtr = 0x01, /* Data Terminal Ready */
Rts = 0x02, /* Ready To Send */ Rts = 0x02, /* Ready To Send */
Out1 = 0x04, /* no longer in use */ Out1 = 0x04, /* no longer in use */
// Ie = 0x08, /* IRQ Enable (cd_sts_ch on omap) */ Out2 = 0x08,
Dm = 0x10, /* Diagnostic Mode loopback */ Dm = 0x10, /* Diagnostic Mode loopback */
}; };
@ -439,14 +438,7 @@ i8250kick(Uart* uart)
int i; int i;
Ctlr *ctlr; Ctlr *ctlr;
/* nothing more to send? then disable xmit intr */
ctlr = uart->regs; ctlr = uart->regs;
if (uart->op >= uart->oe && qlen(uart->oq) == 0 &&
csr8r(ctlr, Lsr) & Temt) {
ctlr->sticky[Ier] &= ~Ethre;
csr8w(ctlr, Ier, 0);
return;
}
/* /*
* 128 here is an arbitrary limit to make sure * 128 here is an arbitrary limit to make sure
@ -460,8 +452,6 @@ i8250kick(Uart* uart)
if(uart->op >= uart->oe && uartstageoutput(uart) == 0) if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
break; break;
csr8o(ctlr, Thr, *uart->op++); /* start tx */ csr8o(ctlr, Thr, *uart->op++); /* start tx */
ctlr->sticky[Ier] |= Ethre;
csr8w(ctlr, Ier, 0); /* intr when done */
} }
} }
@ -602,15 +592,14 @@ i8250enable(Uart* uart, int ie)
intrenable(ctlr->irq, i8250interrupt, uart, 0, uart->name); intrenable(ctlr->irq, i8250interrupt, uart, 0, uart->name);
ctlr->iena = 1; ctlr->iena = 1;
} }
ctlr->sticky[Ier] = Erda; ctlr->sticky[Ier] = Ethre|Erda;
// ctlr->sticky[Mcr] |= Ie; /* not on omap */
ctlr->sticky[Mcr] = 0; ctlr->sticky[Mcr] = 0;
} }
else{ else{
ctlr->sticky[Ier] = 0; ctlr->sticky[Ier] = 0;
ctlr->sticky[Mcr] = 0; ctlr->sticky[Mcr] = 0;
} }
csr8w(ctlr, Ier, 0); csr8w(ctlr, Ier, ctlr->sticky[Ier]);
csr8w(ctlr, Mcr, 0); csr8w(ctlr, Mcr, 0);
(*uart->phys->dtr)(uart, 1); (*uart->phys->dtr)(uart, 1);