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pc, pc64: refactor pcibios code so we dont pollute the amd64 kernel

Browse source 
We can move the pcibios code to its own module
and just provide a stub pcibiosinit() function
for pc64 so we do not have to pull in that code
and the data structures.

also lets us clean up mkdevlist hacks.
This commit is contained in:
cinap_lenrek 2024-11-15 23:20:28 +00:00
parent 6b8c36d51f
commit 705638e189
12 changed files with 127 additions and 142 deletions
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2
sys/src/9/pc/bios32.c
View file

@ -71,7 +71,7 @@ bios32locate(void)
}
void
BIOS32close(BIOS32si* si)
bios32close(BIOS32si* si)
{
vunmap(si->base, si->length);
free(si);

1
sys/src/9/pc/fns.h
View file

@ -113,6 +113,7 @@ void outl(int, ulong);
void outsl(int, void*, int);
ulong paddr(void*);
void patwc(void*, int);
int pcibiosinit(int*, int*);
void pcicfginit(void);
int (*pcicfgrw8)(int, int, int, int);
int (*pcicfgrw16)(int, int, int, int);

1
sys/src/9/pc/mkfile
View file

@ -137,6 +137,7 @@ etherm10g.$O: etherm10g2k.i etherm10g4k.i
etherwpi.$O: ../port/wifi.h
etherrt2860.$O: ../port/wifi.h
l.$O rebootcode.$O apbootstrap.$O: mem.h
pcipc.$O pcibios.$O: ../port/pci.h io.h
initcode.out: init9.$O initcode.$O /$objtype/lib/libc.a
$LD -l -R1 -s -o $target $prereq

2
sys/src/9/pc/pc
View file

@ -96,7 +96,7 @@ link
pmmc pci
misc
pci pcipc
pci pcipc pcibios bios32
archgeneric devkbd i8259 i8253
archacpi mp apic squidboy ec hpet

107
sys/src/9/pc/pcibios.c Normal file
View file

@ -0,0 +1,107 @@
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/pci.h"
static BIOS32si* pcibiossi;
static int
pcicfgrw8bios(int tbdf, int rno, int data, int read)
{
BIOS32ci ci;
memset(&ci, 0, sizeof(BIOS32ci));
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
ci.edi = rno;
if(read){
ci.eax = 0xB108;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return ci.ecx & 0xFF;
}
else{
ci.eax = 0xB10B;
ci.ecx = data & 0xFF;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return 0;
}
return -1;
}
static int
pcicfgrw16bios(int tbdf, int rno, int data, int read)
{
BIOS32ci ci;
memset(&ci, 0, sizeof(BIOS32ci));
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
ci.edi = rno;
if(read){
ci.eax = 0xB109;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return ci.ecx & 0xFFFF;
}
else{
ci.eax = 0xB10C;
ci.ecx = data & 0xFFFF;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return 0;
}
return -1;
}
static int
pcicfgrw32bios(int tbdf, int rno, int data, int read)
{
BIOS32ci ci;
memset(&ci, 0, sizeof(BIOS32ci));
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
ci.edi = rno;
if(read){
ci.eax = 0xB10A;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return ci.ecx;
}
else{
ci.eax = 0xB10D;
ci.ecx = data;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return 0;
}
return -1;
}
int
pcibiosinit(int *maxdno, int *maxbno)
{
BIOS32ci ci;
pcibiossi = bios32open("$PCI");
if(pcibiossi == nil)
return -1;
memset(&ci, 0, sizeof(BIOS32ci));
ci.eax = 0xB101;
if(bios32ci(pcibiossi, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
bios32close(pcibiossi);
pcibiossi = nil;
return -1;
}
if(ci.eax & 0x01)
*maxdno = 31;
else
*maxdno = 15;
*maxbno = ci.ecx & 0xff;
pcicfgrw8 = pcicfgrw8bios;
pcicfgrw16 = pcicfgrw16bios;
pcicfgrw32 = pcicfgrw32bios;
return 0;
}

108
sys/src/9/pc/pcipc.c
View file

@ -23,7 +23,6 @@ static int pcimaxbno = 255;
static int pcicfgmode = -1;
static Pcidev* pciroot;
static int nobios, nopcirouting;
static BIOS32si* pcibiossi;
static int pcicfgrw8raw(int, int, int, int);
static int pcicfgrw16raw(int, int, int, int);
@ -126,108 +125,6 @@ pcicfgrw32raw(int tbdf, int rno, int data, int read)
return data;
}
static int
pcicfgrw8bios(int tbdf, int rno, int data, int read)
{
BIOS32ci ci;
if(pcibiossi == nil)
return -1;
memset(&ci, 0, sizeof(BIOS32ci));
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
ci.edi = rno;
if(read){
ci.eax = 0xB108;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return ci.ecx & 0xFF;
}
else{
ci.eax = 0xB10B;
ci.ecx = data & 0xFF;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return 0;
}
return -1;
}
static int
pcicfgrw16bios(int tbdf, int rno, int data, int read)
{
BIOS32ci ci;
if(pcibiossi == nil)
return -1;
memset(&ci, 0, sizeof(BIOS32ci));
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
ci.edi = rno;
if(read){
ci.eax = 0xB109;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return ci.ecx & 0xFFFF;
}
else{
ci.eax = 0xB10C;
ci.ecx = data & 0xFFFF;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return 0;
}
return -1;
}
static int
pcicfgrw32bios(int tbdf, int rno, int data, int read)
{
BIOS32ci ci;
if(pcibiossi == nil)
return -1;
memset(&ci, 0, sizeof(BIOS32ci));
ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
ci.edi = rno;
if(read){
ci.eax = 0xB10A;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return ci.ecx;
}
else{
ci.eax = 0xB10D;
ci.ecx = data;
if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
return 0;
}
return -1;
}
static BIOS32si*
pcibiosinit(void)
{
BIOS32ci ci;
BIOS32si *si;
if((si = bios32open("$PCI")) == nil)
return nil;
memset(&ci, 0, sizeof(BIOS32ci));
ci.eax = 0xB101;
if(bios32ci(si, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
free(si);
return nil;
}
if(ci.eax & 0x01)
pcimaxdno = 31;
else
pcimaxdno = 15;
pcimaxbno = ci.ecx & 0xff;
return si;
}
static uchar
pIIxget(Pcidev *router, uchar link)
{
@ -673,11 +570,8 @@ pcicfginit(void)
}
if(pcicfgmode < 0 || pcibios) {
if((pcibiossi = pcibiosinit()) == nil)
if(pcibiosinit(&pcimaxdno, &pcimaxbno) < 0)
goto out;
pcicfgrw8 = pcicfgrw8bios;
pcicfgrw16 = pcicfgrw16bios;
pcicfgrw32 = pcicfgrw32bios;
pcicfgmode = 3;
}

12
sys/src/9/pc64/dat.h
View file

@ -1,5 +1,3 @@
typedef struct BIOS32si BIOS32si;
typedef struct BIOS32ci BIOS32ci;
typedef struct Conf Conf;
typedef struct Confmem Confmem;
typedef struct FPssestate FPssestate;
@ -23,7 +21,6 @@ typedef vlong Tval;
typedef struct Ureg Ureg;
typedef struct Vctl Vctl;
#pragma incomplete BIOS32si
#pragma incomplete Pcidev
#pragma incomplete Ureg
@ -352,12 +349,3 @@ struct DevConf
int nports; /* Number of ports */
Devport *ports; /* The ports themselves */
};
typedef struct BIOS32ci { /* BIOS32 Calling Interface */
u32int eax;
u32int ebx;
u32int ecx;
u32int edx;
u32int esi;
u32int edi;
} BIOS32ci;

5
sys/src/9/pc64/fns.h
View file

@ -3,10 +3,6 @@
Dirtab* addarchfile(char*, int, long(*)(Chan*,void*,long,vlong), long(*)(Chan*,void*,long,vlong));
void archinit(void);
void archreset(void);
int bios32call(BIOS32ci*, u16int[3]);
int bios32ci(BIOS32si*, BIOS32ci*);
void bios32close(BIOS32si*);
BIOS32si* bios32open(char*);
void bootargsinit(void);
uintptr cankaddr(uintptr);
int checksum(void *, int);
@ -117,6 +113,7 @@ void outl(int, ulong);
void outsl(int, void*, int);
uintptr paddr(void*);
void patwc(void*, int);
int pcibiosinit(int*, int*);
void pcicfginit(void);
int (*pcicfgrw8)(int, int, int, int);
int (*pcicfgrw16)(int, int, int, int);

8
sys/src/9/pc64/l.s
View file

@ -421,14 +421,6 @@ TEXT mb586(SB), 1, $-4
CPUID
RET
/*
* BIOS32.
*/
TEXT bios32call(SB), 1, $-4
XORL AX, AX
INCL AX
RET
/*
* Basic timing loop.
*/

7
sys/src/9/pc64/main.c
View file

@ -364,3 +364,10 @@ procsave(Proc *p)
*/
mmuflushtlb(PADDR(m->pml4));
}
int
pcibiosinit(int *, int *)
{
return -1;
}

2
sys/src/9/pc64/mkfile
View file

@ -141,6 +141,8 @@ ethervt6105m.$O: ../port/ethermii.h
etherwpi.$O: ../port/wifi.h
etherrt2860.$O: ../port/wifi.h
pcipc.$O: ../port/pci.h io.h
initcode.out: init9.$O initcode.$O /$objtype/lib/libc.a
$LD -l -R1 -s -o $target $prereq

14
sys/src/9/port/mkdevlist
View file

@ -1,6 +1,6 @@
#!/bin/rc
awk -v 'objtype='$objtype '
awk '
BEGIN{
if(ARGC < 2)
exit;
@ -18,12 +18,12 @@ collect && /^[^ \t]/{
}
collect && $0 ~ /[^ \t]+/{
if(isdev)
obj["dev" $1 "'.$O'"]++;
obj["dev" $1]++;
else
obj[$1 "'.$O'"]++;
obj[$1]++;
for(i = 2; i <= NF; i++){
if($i !~ "[+=-].*")
obj[$i "'.$O'"]++;
obj[$i]++;
}
}
$0 ~ /^[^ \t]/{
@ -37,10 +37,6 @@ $0 ~ /^[^ \t]/{
}
END{
x = ""
for(i in obj)
x = x i "\n";
if((objtype ~ "386" || objtype ~ "amd64") && obj["pci" "'.$O'"])
x = x "bios32'.$O' \n";
printf x;
print i ".'$O'"
}' $*