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git://git.9front.org/plan9front/plan9front
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pi3: implement sdhost controller driver so we can use wifi always
This commit is contained in:
cinap_lenrek
parent
019a935f6b
commit
9b68b42610
2 changed files with 260 additions and 1 deletions
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@ -28,11 +28,12 @@ dev
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link
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archbcm3
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usbdwc
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# ether4330
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ether4330
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ethermedium
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loopbackmedium
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netdevmedium
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emmc
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sdhost
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# i2cbcm devi2c
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i2cgpio devi2c gpio
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258
sys/src/9/bcm64/sdhost.c
Normal file
258
sys/src/9/bcm64/sdhost.c
Normal file
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@ -0,0 +1,258 @@
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/*
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* bcm2835 sdhost controller
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*/
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#include "u.h"
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#include "../port/lib.h"
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#include "../port/error.h"
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#include "mem.h"
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#include "dat.h"
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#include "fns.h"
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#include "io.h"
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#include "../port/sd.h"
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#define SDHOSTREGS (VIRTIO+0x202000)
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enum {
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HC_COMMAND = 0x00>>2,
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HC_CMD_ENABLE = 0x8000,
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HC_CMD_FAILED = 0x4000,
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HC_CMD_BUSY = 0x0800,
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HC_CMD_RESPONSE_NONE = 0x0400,
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HC_CMD_RESPONSE_LONG = 0x0200,
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HC_CMD_WRITE = 0x0080,
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HC_CMD_READ = 0x0040,
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HC_CMD_MASK = 0x003F,
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HC_ARGUMENT = 0x04>>2,
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HC_TIMEOUTCOUNTER = 0x08>>2,
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HC_CLOCKDIVISOR = 0x0c>>2,
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HC_CLKDIV_MAX = 0x07FF,
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HC_RESPONSE_0 = 0x10>>2,
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HC_RESPONSE_1 = 0x14>>2,
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HC_RESPONSE_2 = 0x18>>2,
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HC_RESPONSE_3 = 0x1c>>2,
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HC_HOSTSTATUS = 0x20>>2,
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HC_HSTST_HAVE_DATA = 0x0001,
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HC_HSTST_ERROR_FIFO = 0x0008,
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HC_HSTST_ERROR_CRC7 = 0x0010,
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HC_HSTST_ERROR_CRC16 = 0x0020,
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HC_HSTST_TIMEOUT_CMD = 0x0040,
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HC_HSTST_TIMEOUT_DATA = 0x0080,
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HC_HSTST_INT_BLOCK = 0x0200,
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HC_HSTST_INT_BUSY = 0x0400,
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HC_HSTST_RESET = 0xFFFF,
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HC_HSTST_ERROR
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= HC_HSTST_ERROR_FIFO
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| HC_HSTST_ERROR_CRC7
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| HC_HSTST_ERROR_CRC16
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| HC_HSTST_TIMEOUT_CMD
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| HC_HSTST_TIMEOUT_DATA,
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HC_POWER = 0x30>>2,
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HC_DEBUG = 0x34>>2,
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HC_HOSTCONFIG = 0x38>>2,
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HC_HSTCF_INTBUS_WIDE = 0x0002,
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HC_HSTCF_EXTBUS_4BIT = 0x0004,
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HC_HSTCF_SLOW_CARD = 0x0008,
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HC_HSTCF_INT_DATA = 0x0010,
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HC_HSTCF_INT_BLOCK = 0x0100,
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HC_HSTCF_INT_BUSY = 0x0400,
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HC_BLOCKSIZE = 0x3C>>2,
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HC_DATAPORT = 0x40>>2,
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HC_BLOCKCOUNT = 0x50>>2,
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};
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static u32int
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RD(int reg)
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{
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u32int *r = (u32int*)SDHOSTREGS;
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coherence();
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return r[reg];
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}
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static void
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WR(int reg, u32int val)
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{
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u32int *r = (u32int*)SDHOSTREGS;
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if(0)print("WR %2.2ux %ux\n", reg<<2, val);
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coherence();
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r[reg] = val;
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}
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static void
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sdhostclk(uint freq)
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{
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uint div, ext;
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ext = getclkrate(ClkCore);
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div = freq / ext;
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if(div < 2)
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div = 2;
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if((ext / div) > freq)
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div++;
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div -= 2;
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if(div > HC_CLKDIV_MAX)
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div = HC_CLKDIV_MAX;
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freq = ext / (div+2);
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WR(HC_CLOCKDIVISOR, div);
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WR(HC_TIMEOUTCOUNTER, freq/2); /* 500ms timeout */
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}
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static void
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sdhostbus(SDio*, int width, int speed)
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{
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switch(width){
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case 1:
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WR(HC_HOSTCONFIG, RD(HC_HOSTCONFIG) & ~HC_HSTCF_EXTBUS_4BIT);
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break;
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case 4:
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WR(HC_HOSTCONFIG, RD(HC_HOSTCONFIG) | HC_HSTCF_EXTBUS_4BIT);
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break;
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}
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if(speed)
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sdhostclk(speed);
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}
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static int
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sdhostinit(SDio*)
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{
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WR(HC_POWER, 0);
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WR(HC_COMMAND, 0);
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WR(HC_ARGUMENT, 0);
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WR(HC_TIMEOUTCOUNTER, 0);
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WR(HC_CLOCKDIVISOR, 0);
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WR(HC_HOSTSTATUS, HC_HSTST_RESET);
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WR(HC_HOSTCONFIG, 0);
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WR(HC_BLOCKSIZE, 0);
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WR(HC_BLOCKCOUNT, 0);
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microdelay(20);
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return 0;
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}
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static int
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sdhostinquiry(SDio *, char *inquiry, int inqlen)
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{
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return snprint(inquiry, inqlen, "BCM SD Host Controller");
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}
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static void
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sdhostenable(SDio *io)
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{
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WR(HC_POWER, 1);
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WR(HC_HOSTCONFIG, HC_HSTCF_INTBUS_WIDE|HC_HSTCF_SLOW_CARD);
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sdhostclk(25*Mhz);
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}
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static void
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sdhosterror(u32int i)
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{
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snprint(up->genbuf, sizeof(up->genbuf), "sdhost error %#ux\n", i);
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error(up->genbuf);
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}
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static int
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sdhostcmd(SDio*, SDiocmd *cmd, u32int arg, u32int *resp)
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{
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u32int c, i;
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ulong now;
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c = cmd->index & HC_CMD_MASK;
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switch(cmd->resp){
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case 0:
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c |= HC_CMD_RESPONSE_NONE;
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break;
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case 1:
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if(cmd->busy)
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c |= HC_CMD_BUSY;
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default:
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break;
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case 2:
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c |= HC_CMD_RESPONSE_LONG;
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break;
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}
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if(cmd->data){
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if(cmd->data & 1)
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c |= HC_CMD_READ;
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else
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c |= HC_CMD_WRITE;
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}
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/* clear errors */
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WR(HC_HOSTSTATUS, RD(HC_HOSTSTATUS));
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WR(HC_ARGUMENT, arg);
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WR(HC_COMMAND, c | HC_CMD_ENABLE);
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now = MACHP(0)->ticks;
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while((i = RD(HC_COMMAND)) & HC_CMD_ENABLE)
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if(MACHP(0)->ticks - now > HZ)
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break;
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if(i & HC_CMD_ENABLE)
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error("command never completed");
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if(i & HC_CMD_FAILED)
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error("command failed");
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if((i = RD(HC_HOSTSTATUS)) & HC_HSTST_ERROR)
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sdhosterror(i);
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if(c & HC_CMD_RESPONSE_NONE) {
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resp[0] = 0;
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} else if(c & HC_CMD_RESPONSE_LONG) {
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resp[0] = RD(HC_RESPONSE_0);
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resp[1] = RD(HC_RESPONSE_1);
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resp[2] = RD(HC_RESPONSE_2);
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resp[3] = RD(HC_RESPONSE_3);
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} else {
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resp[0] = RD(HC_RESPONSE_0);
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}
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return 0;
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}
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static void
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sdhostiosetup(SDio*, int write, void *buf, int bsize, int bcount)
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{
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WR(HC_BLOCKSIZE, bsize);
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WR(HC_BLOCKCOUNT, bcount);
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}
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static void
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sdhostio(SDio*, int write, uchar *buf, int len)
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{
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u32int i, *r = (u32int*)SDHOSTREGS;
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if(write)
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dmastart(DmaChanSdhost, DmaDevSdhost, DmaM2D, buf, r + HC_DATAPORT, len);
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else
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dmastart(DmaChanSdhost, DmaDevSdhost, DmaD2M, r + HC_DATAPORT, buf, len);
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if(dmawait(DmaChanSdhost) < 0)
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error(Eio);
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if((i = RD(HC_HOSTSTATUS)) & HC_HSTST_ERROR)
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sdhosterror(i);
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}
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void
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sdhostlink(void)
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{
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static SDio io = {
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"sdhost",
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sdhostinit,
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sdhostenable,
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sdhostinquiry,
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sdhostcmd,
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sdhostiosetup,
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sdhostio,
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sdhostbus,
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};
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addmmcio(&io);
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}
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